Keyword: FPGA
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MOOB04 Upgrade of the Machine Protection System Toward 1.3 MW Operation of the J-PARC Neutrino Beamline target, proton, operation, electron 18
 
  • K. Sakashita, M.L. Friend, K. Nakayoshi
    KEK, Ibaraki, Japan
  • Y. Koshio, S. Yamasu
    Okayama University, Faculty of Science, Okayama City, Japan
 
  The machine protection system (MPS) is one of the essential components to realize safe operation of the J-PARC neutrino beamline, where a high intensity neutrino beam for the T2K long baseline neutrino oscillation experiment is generated by striking 30GeV protons on a graphite target. The proton beam is extracted from the J-PARC main ring proton synchrotron (MR) into the primary beamline. The beamline is currently operated with 485kW MR beam power. The MR beam power is planned to be upgraded to 1.3+ MW. The neutrino production target could be damaged if the high intensity beam hits off-centered on the target, due to non-uniform thermal stress. Therefore, in order to protect the target, it is important to immediately stop the beam when the beam orbit is shifted. A new FPGA-based interlock module, with which the beam profile is calculated in real time, was recently developed and commissioned. This module reads out signals from a titanium-strip-based secondary emission profile monitor (SSEM) which is placed in the primary beamline. An overview of the upgrade plan of the MPS system and the results of an initial evaluation test of the new interlock module will be discussed.  
slides icon Slides MOOB04 [8.367 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-MOOB04  
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TUOC01 Integration of a Pilot-Tone Based BPM System Within the Global Orbit Feedback Environment of Elettra controls, electron, Ethernet, feedback 190
 
  • G. Brajnik, S. Bassanese, G. Cautero, S. Cleva, R. De Monte
    Elettra-Sincrotrone Trieste S.C.p.A., Basovizza, Italy
 
  In this contribution, we describe the advantages of the pilot tone compensation technique that we implemented in a new BPM prototype for Elettra 2.0. Injecting a fixed reference tone upstream of cables allows for a continuous calibration of the system, compensating the different behaviour of every channel due to thermal drifts, variations of cable properties, mismatches and tolerances of components. The system ran successfully as a drop-in substitute for a Libera Electron not only during various machine shifts, but also during a user dedicated beamtime shift for more than 10 hours, behaving in a transparent way for all the control systems and users. The equivalent RMS noise (at 10 kHz data rate) for the pilot tone position was less than 200 nm on a 19 mm vacuum chamber radius, with a long-term stability better than 1 um in a 12-hour window. Two main steps led to this important result: firstly, the development of a novel RF front end that adds the pilot tone to the signals originated by the beam, secondly, the realisation of an FPGA-based double digital receiver that demodulates both beam and pilot amplitudes, calculating the compensated X and Y positions.  
slides icon Slides TUOC01 [6.468 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-TUOC01  
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TUOC03 Commissioning of the Open Source Sirius BPM Electronics electron, electronics, controls, Ethernet 196
 
  • S.R. Marques, G.B.M. Bruno, L.M. Russo, H.A. Silva, D.O. Tavares
    LNLS, Campinas, Brazil
 
  The new Brazilian 4th generation light source, Sirius, have already started and commissioning is planned to start in 2018. This paper will report on the manufacturing, deployment and production batch testing of the in-house developed BPM electronics. The latest performance and reliability achievements will be presented.  
slides icon Slides TUOC03 [14.606 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-TUOC03  
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TUPA16 Signal Processing for Beam Loss Monitor System at Jefferson Lab machine-protect, controls, operation, diagnostics 245
 
  • J. Yan, T.L. Allison, S. Bruhwel, W. Lu
    JLab, Newport News, Virginia, USA
 
  Funding: Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177.
Ion Chamber and Photomultiplier Tube (PMT) were both used for beam loss monitor in the Machine Protection System (MPS) at Jefferson Lab. The requirements of signal processing of these detectors are different, so two VME-based signal processing boards, Beam Loss Monitor (BLM) board and Ion-Chamber board, were developed. The BLM board has fast response (< 1us) and 5 decades dynamic range from 10nA to 1 mA, while the Ion-Chamber board has 8 decades dynamic range from 100 pA to 10 mA and slower response. Both of boards provide functions of machine protection and beam diagnostics, and have features of fast shutdown (FSD) interface, beam sync interface, built-in-self-test, remotely controlled bias signals, and on-board memory buffer.
 
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-TUPA16  
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THOA01 Low vs High Level Programming for FPGA interface, operation, experiment, software 527
 
  • J. Marjanovic
    DESY, Hamburg, Germany
 
  From their introduction in the eighties, Field-Programmable Gate Arrays (FPGAs) have grown in size and performance for several orders of magnitude. As the FPGA capabilities have grown, so have the designs. It seems that current tools and languages (VHDL and (System)Verilog) do not match the complexity required for advanced digital signal processing (DSP) systems usually found in experimental physics applications. In the last couple of years several commercial High-Level Synthesis (HLS) tools have emerged, providing a new method to implement FPGA designs, or at least some parts of it. By providing a higher level of abstraction, new tools offer a possibility to express algorithms in a way which is closer to the mathematical description. Such implementation is understood by a broader range of people, and thus minimizes the documentation and communication issues. Several examples of DSP algorithms relevant for beam instrumentation will be presented. Implementations of these algorithms with different HLS tools and traditional implementation in VHDL will be compared.  
slides icon Slides THOA01 [1.873 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2018-THOA01  
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